C128DX for Minimig MiSTer specs and memory map > MiSTer requirements * DE10 MiSTer FPGA * 32mb/64mb/128mb SDRAM expansion (used as Chip RAM) * Up to 384mb Fast RAM from HPS DDR * 4gb potential addressing space > MiSTer recommended * I/O 5.5-6.0 board (any type) > MiSTer optional * USB Hub 1.1 (or 2.0) >> Specifications: > CPU The Kitsunet K85832 "Kuzunoha" chip: Enhanced implementation of WDC 65832 CPU (6502/65816 compatible) * 6510/8502 glue logic for C64/128 compatibility * Real, unmultiplexed 32 bit address/data buses with 4 byte selects * Speeds: * 1mhz with 6510 timing * 2mhz with 8502 timing * 4/8/16mhz with 8502 timing * 20mhz with SuperCPU64/128 timing * 33mhz with K85832 timing (minimal cycles per instruction, fastest possible CPU) * SDRAM operating speed: 133mhz * Extended addressing modes for 32bit access * Programmable Bank Mapper * Full Memory Management/Protection Unit * Extended instruction set (42xx) * Second status register * Unused opcodes on 6502 always map to new 16/32 instructions. > VIC-II - unmodified. We will not be touching the VIC to maximize the C64/128 compatibility. > MMU8732 - MMUv3 "Ariel" chip Pages in and manages up to 4GB memory for 8502 mode Completely compatible with C128 mmu8722 > VIX (Video Interface Expander) "Murrimi" chip - VDC controller version 3 * Up to 1280x800: 320/640/960/1280 x 200/400/600/800 * Monochrome, 16 color, 256 color (or 255 color with alpha), 65536 color (or 32768 color with alpha) * 1 sprite for mouse, 1 blitter * Programmable raster interrupt * Up to 2016KB memory shared with CPU * Memory mapping: * Registers: $D680-$D6FF * Video memory: * Mono, 4, 16 colors: $F80000-$FFBFFF * 8 bit CLUT: $F00000-$FFBFFF * 15/16 bit: $E00000-$FBFFFF > Audio 16581 "Ry'slai" (SID Extreme) * 9x SID Extreme voices * Usual ADSR and Sawtooth/Pulse/Triangle/Noise waveforms * Additional 8/16 bit audio sample modes * 2 recording channels (left/right) * 65280 bytes dedicated SID Ex RAM for recording and SID playback >> Memory Map (Overview) | Types .. SRAM: On FPGA; CHIP: SDRAM; FAST: DDR Contents Addresses Size Type Description ------------------------------------------------------------------[All modes]- CPU RAM $0000FF05-$0000FFFF 250 SRAM Mirror of $FFFFFF05-$FFFFFFFF CPU RAM * $FFFF0000-$FFFFFFFF 64K SRAM CPU control RAM CPU RAM $FFFFFF00-$FFFFFFFF 256 SRAM 8/16/32 mode vectors and bootstrap (copied from ROM) ------------------------------------------------------------[6510 (C64) mode]- CPU IO $ 0000-$ 0001 2 CPU 6510 I/O registers LOW RAM $ 0002-$ 7FFF 16K CHIP TPA: 6510 mode chip RAM GAME $ 8000-$ 9FFF 8K ROM Cartridge ROM | RAM $ 8000-$ 9FFF 8K CHIP RAM BASIC $ A000-$ BFFF 8K ROM BASIC ROM EXROM $ A000-$ BFFF 8K ROM Cartridge ROM | RAM $ A000-$ BFFF 8K CHIP Banked ROMs controlled by MMU RAM $ C000-$ CFFF 4K CHIP RAM IO AREA $ D000-$ DFFF 4K IO C64 I/O Area | RAM $ D000-$ DFFF 4K CHIP RAM KERNEL $ E000-$ FFFF 8K ROM C64 Kernel | RAM $ E000-$ FFFF 8K CHIP RAM -----------------------------------------------------------[8502 (C128) mode]- LOW RAM $ xx0000-$ xx3FFF 16K CHIP TPA: 8502 mode chip RAM - Sharing controlled by MMU BANK RAM $ xx4000-$ xxBFFF 32K CHIP TPA: 8502 mode banked RAM - Page controlled by MMU | BANK ROM $ xx8000-$ xxBFFF 16K ROM Banked ROMs controlled by MMU | BASIC $ xx8000-$ xxBFFF 16K ROM C128 BASIC v7 BANK RAM $ xxC000-$ xxFFFF 16K CHIP TPA: 8502 mode banked RAM - Sharing controlled by MMU | IO AREA $ xxD000-$ xxDFFF 4K IO C128 I/O area | ROM $ xxE000-$ xxFEFF 2032 ROM C128 Kernel MMU $ xxFF00-$ xxFF04 5 MMU MMUv2 configuration switch registers ROM $ xxFF05-$ xxFFFF 251 ROM C128 Kernel BANK RAM $ 000000-$ 00FFFF 64K CHIP C128 Bank $00, Zero Page, Stack, BASIC7 programs BANK RAM $ 010000-$ 01FFFF 64K CHIP C128 Bank $01, BASIC v7 variables BANK RAM $ 020000-$ 03FFFF 128K CHIP C128 Banks $02-03 | MMU Swap banks RAM $ 040000-$ 8FFFFF 8896K CHIP RAM banks $04-$8F RAM $ 090000-$ CFFFFF 4096K CHIP RAM banks $90-$CF & GEORAM $ 090000-$ CFFFFF 4096K CHIP GEORAM Memory ROM $ D00000-$ DFFFFF 1MB ROM C128DX Kernel, OS, BASIC v16 | RAM $ D00000-$ DFFFFF 1MB CHIP RAM banks $D0-$DF RAM $ E00000-$ EFFFFF 1MB CHIP RAM banks $E0-$EF | VDCRAM $ E00000-$ EFFFFF 1MB CHIP VDC RAM (15/16 bit color modes) | I/O $ E00000-$ EFFFFF 1MB IO C128DX I/O area RAM $ F00000-$ FFFFFF 1MB CHIP RAM banks $F0-$FF | VDCRAM $ F00000-$ FF9FFF 1000K CHIP VDC RAM (1/4/8 bit color modes) | VDCRAM $ FFA000-$ FFBFFF 8K CHIP VDC Character data, Mouse pointer CPU $ FFC000-$ FFFFFF 16K SRAM CPU RAM, IDCACHE, Vectors -------------------------------------------------[85832 (C128DX) 16 bit mode]- LOW RAM $ 000000-$ 01FFFF 128K 8502 Same as 8502 mode BANK RAM $ 000000-$ 00FFFF 64K CHIP C128 Bank $00 BANK RAM $ 010000-$ 01FFFF 64K CHIP C128 Bank $01 BANK RAM $ 020000-$ 02FFFF 64K CHIP C128 Bank $02 | DirectPG $ 020000-$ 02xxxx 64K > CHIP C128DX: K85816 Direct Page | Stack $ 02xxxx-$ 02FFFF 64K < CHIP C128DX: K85816 Stack | MMU $ 020000-$ 02FFFF 64K CHIP C128 MMU swappable page / task switch BANK RAM $ 030000-$ 03FFFF 64K CHIP C128 mode bank 3 | MMU Swap Bank RAM $ 040000-$ 8FFFFF 8896K CHIP RAM banks $04-$8F RAM $ 090000-$ CFFFFF 4096K CHIP RAM banks $90-$CF & GEORAM $ 090000-$ CFFFFF 4096K CHIP GEORAM Memory ROM $ D00000-$ DFFFFF 1MB ROM C128DX Kernel, OS, BASIC v16 | RAM $ D00000-$ DFFFFF 1MB CHIP RAM banks $D0-$DF RAM $ E00000-$ EFFFFF 1MB CHIP RAM banks $E0-$EF | VDCRAM $ E00000-$ EFFFFF 1MB CHIP VDC RAM (15/16 bit color modes) | I/O $ E00000-$ EFFFFF 1MB IO C128DX I/O area RAM $ F00000-$ FFFFFF 1MB CHIP RAM banks $FF-$FF | VDCRAM $ F00000-$ FF9FFF 1000K CHIP VDC RAM (1/4/8 bit color modes) | VDCRAM $ FFA000-$ FFBFFF 8K CHIP VDC Character data, Mouse pointer CPU $ FFC000-$ FFFFFF 16K SRAM CPU RAM, IDCACHE, Vectors ------------------------------------------------------------------------------ To attempt some level of compatibility, the C128DX attempts to closely mirror the Mega65 I/O memory map and the memory map above the 16MB (24 bit) mark. ----------------------------------------------------------[85832 32 bit mode]- LOW RAM $00000000-$00FFFFFF 16MB 85816 8/16 bit mode use - 32MB MiSTer SDRAM MID RAM $01000000-$01FFFFFF 16MB CHIP C128DX Chip RAM - 32MB MiSTer SDRAM & REU $01000000-$01FFFFFF 16MB CHIP REU RAM - 32MB MiSTer SDRAM RAM64 $02000000-$03FFFFFF 32MB CHIP C128DX Chip RAM - 64MB MiSTer SDRAM RAM128 $04000000-$07FFFFFF 64MB CHIP C128DX Chip RAM - 128MB MiSTer SDRAM MEGA65 $08000000-$08FFFFFF 16MB CHIP Mirror of $02xxxxxx - 64MB MiSTer SDRAM & ATTIC $08000000-$087FFFFF 8MB CHIP C65/Mega65 Attic RAM - 64MB MiSTer SDRAM & CELLAR $08800000-$08FFFFFF 8MB CHIP C65/Mega65 Cellar RAM - 64MB MiSTer SDRAM $10000000-$27FFFFFF 384MB FAST HPS DDR3 RAM $28000000-$2FFFFFFF 128MB ROM HPS I/O RAM (Visible only) $30000000-$3FFFFFFF 256MB VIRT Disk mapped RAM/ROM/Swap RESERVED $40000000-$BFFFFFFF 2GB VIRT Mirrors of $00000000-$3FFFFFFF RESERVED $C0000000-$DFFFFFFF 2GB NIL Reads as 00 55 AA FF .. HIGH IO $E0000000-$EFFFFFFF 256MB PCI PCI and PCI-e expansions HIGH ROM $F0000000-$FEFFFFFF 240MB ROM Future expansions HIGH ROM $FF000000-$FFFEFFFF 16128K ROM Future expansions CPU RAM $FFFF0000-$FFFFFFFF 64K SRAM CPU RAM (see CPU spec) ------------------------------------------------------------------------------ CPU RAM: SRAM or FPGA BRAM, accessible any time. CHIP RAM: Must be readable or writable on a per cycle basis. FAST RAM: Can wait for multiple cycles, should be accessed 32 bits at a time. I/O map: $Dxxx $D0xx : VIC-II - Literally see any VIC-II register map $D1xx ------------- C128DX "Murrimi" VIX VDC --------------------------------- $D1xx : $D2xx : $D3xx : $D4xx ------------- 16581 "Ry'slai" SID Extreme sound chip ------------------- $D400 32 VSID1 6581/8580 register map emulation (default left channel) $D400 7 VS1V1 Voice 1 (center) (ring/modulate with voice 3) $D407 7 VS1V2 Voice 2 (center) (ring/modulate with voice 1) $D40E 7 VS1V3 Voice 3 (center) (ring/modulate with voice 2) $D415 1 VS1FCL Filter cutoff frequency low byte $D416 1 VS1FCH 7: 0:6581 filtering 1: 8580 filtering 6-4: Digi volume boost (0-7) 3-0: Filter cutoff frequency high nybble $D417 1 VS1FRR Filter resonance and routing 7-4: Resonance 3: External input 2: Voice 3 1: Voice 2 0: Voice 1 $D418 1 VS1VOL Filter mode and volume 7: Mute voice 3 6: High pass 5: Band pass 4: Low pass 3-0: Volume control (high nybble) $D419 1 VS1OSC1 Voice 1 oscillator $D41A 1 VS1ENV1 Voice 1 envelope $D41B 1 VS1OSC3 Voice 3 oscillator $D41C 1 VS1ENV3 Voice 3 envelope $D41D 1 VS1OSC2 Voice 2 oscillator $D41E 1 VS1ENV2 Voice 2 envelope $D41F 1 VS1VOLX 7-4: Voice pan (0: left channel, 8: center, 15: right channel) 3-0: Volume control (low nybble) $D420 32 VSID2 6581/8580 register map emulation (default right channel [AS ABOVE except +$20]) $D420 7 VS2V4 Voice 4 (left) (ring/modulate with voice 6) $D427 7 VS2V5 Voice 5 (left) (ring/modulate with voice 4) $D42E 7 VS2V6 Voice 6 (left) (ring/modulate with voice 5) $D440 32 VSID3 6581/8580 register map emulation (default backleft channel [AS ABOVE except +$40]) $D440 7 VS3V7 Voice 7 (left) (ring/modulate with voice 9) $D447 7 VS3V8 Voice 8 (left) (ring/modulate with voice 7) $D44E 7 VS3V9 Voice 9 (left) (ring/modulate with voice 8) $D460 32 VSID4 6581/8580 register map emulation (default right channel [AS ABOVE except +$40]) $D460 7 VS4VA Voice 10 (left) (ring/modulate with voice 12) $D467 7 VS4VB Voice 11 (left) (ring/modulate with voice 10) $D46E 7 VS4VC Voice 12 (left) (ring/modulate with voice 11) $D480 16 VS1VD SID Extreme Voice 13 (default left channel) VSID1 $D490 16 VS1VE SID Extreme Voice 14 (default left channel) VSID1 $D4A0 16 VS2VF SID Extreme Voice 15 (default right channel) VSID2 $D4B0 16 VS2VG SID Extreme Voice 16 (default right channel) VSID2 $D4C0 16 VS3VH SID Extreme Voice 17 (default back-left channel) VSID3 $D4D0 16 VS3VI SID Extreme Voice 18 (default back-left channel) VSID3 $D4E0 16 VS4VJ VSSID Extreme Voice 19 (default back-right channel) VSID4 $D4F0 16 VS4VK SID Extreme Voice 20 (default back-right channel) VSID4 > Voice registers ($D4x0, $D4x7, $D4xE, where x = 0,2,4,6) +$00 2 VFRQ Voice frequency (for RAW samples should be set equal to 02 UNLESS intentionally pitch skewing) +$02 2 VPDC Voice pulse wave duty cycle (pulse waveform) OR +$02 2 VRBF Voice RAW base frequency (Frequency that wave sample was encoded at) +$04 1 VCR Voice control register 7: Noise 6: Pulse 5: Sawtooth 4: Triangle 3: RAW 2: Modulate 1: Synchronize 0: Gate +$05 1 VAD Voice Attack/Decay 7-4: Attack 3-0: Decay +$06 1 VSR Voice Sustain/Release 7-4: Sustain 3-0: Release > Voice extended registers (on voices 13-20 at $D4x7, where x = 8-F) +$07 1 VECR1 Voice extended control register 7: 0: RAW one shot (Play sample once then stop) 1: RAW continuous (Repeat sample) 6: 0: 6581 filtering 1: 8580 filtering 3: Voice bitness (0:8 bit, 1:16 bit) 1: Continuation register: 0: Changes to $08-0C take place immediately. 1: Changes to $08-0C take place when current sample finishes (use to play more than 64kb samples) 0: 0: Immediately terminate playback of sample 1: Start playback of sample from beginning +$08 4 VRADR Location in CHIP RAM of RAW sample +$0C 2 VRLEN Length of sample (up to 64kb) +$0E 1 VRVOL Volume adjustment of left/right channel 7-4: (Left channel: 0=Mute, F=Full) 3-0: (Left channel: 0=Mute, F=Full) +$0F 1 VECR2 Voice extended control register 2 7: Mute, terminate, and reset channel to defaults 6: 1: Retrieve sample information before playback: Bytes 00-01 to register 02 (Sample frequency) Bytes 02-03 to register 0B (Sample length) Byte 04 bit 0 to register 07 bit 3 (Sample bitness) If Byte 04 bit 7 set: (For more information) Byte 04 bit 1 to byte 07 bit 7 (Set whether one shot or continuous) Byte 05 to register 0D (Set left default volume) Byte 06 to register 0E (Set right default volume) If Byte 04 bit 6 set: Byte 07-08 to reg 00-01 (Sets target frequency) Else: Reg 02-03 cloned to 00-01 (sets base and target frequency the same [no pitch change]) If Byte 04 bit 0 set: Playback started at byte 0A (byte 09 reserved and ignored) Else: Playback will start at byte 0A when triggered ($07 bit 0) 0: Do not retrieve sample information, assumed manually set, playback will begin at byte 00 3-0: Voice that Modulate/Synchronize operates with $D5xx ------------- C128DX 8732 "Ariel" 32 bit MMU --------------------------- $D500 1 MMUCR1 Configuration register 7-6 MMU bank mapped to CPU (0-3) 5-4 ROM HI mapping (00=System; 01=IntRom; 10=ExtRom; 11=RAM) 3-2 ROM MID mapping (00=System; 01=IntRom; 10=ExtRom; 11=RAM) 1 ROM LOW mapping (0=System; 1=RAM) 0 I/O at $D000 (1=Yes; 0=No) $D501 1 PCRA Preconfiguration register A as above (triggered at FF01) $D502 1 PCRB Preconfiguration register B as above (triggered at FF02) $D503 1 PCRC Preconfiguration register C as above (triggered at FF03) $D504 1 PCRD Preconfiguration register D as above (triggered at FF04) $D505 1 MMUMCR Mode configuration register 7 40/80 key sense (1=80; 0=40) 6 OS mode (0=C128; 1=C64) 5 /EXROM sense 4 /GAME sense 3 FSDIR 2 Unused 1 Unused 0 Processor (0=8502; 1=85832) $D506 1 MMURCR RAM configuration register 7-6 VIC RAM Bank (0-3) 5-4 MMU v1 ExRAM (0=Pages 0-3; 1=Pages 4-7; 2=Pages 8-11; 3=Pages 12-15) 3-2 RAM share status (0=None; 1=Top; 2=Bottom; 3=Both) 1-0 RAM share amount (0=1k; 1=4k; 2=8k; 3=16k) $D507 1 MMUP0L Zero page pointer low (nn = xxnn00-xxnnFF) $D508 1 MMUP0H Zero page pointer high (nn = nnxx00-nnxxFF) $D509 1 MMUP1L Stack page pointer low (nn = xxnn00-xxnnFF) $D50A 1 MMUP1H Stack page pointer high (nn = nnxx00-nnxxFF) $D50B 1 MMUVER MMU Bank and version # 7-4 Banks nnnn = 2^(nnnn) banks (1=128k; 2=256k; 4=1MB; 8=16MB; 15=2GB) 3-0 MMU Version (0=Stock; 1=ExRAM available (1mb); 2=Page2/3 4GB paging available) $D50C 1 MMUPG0L RAM bank LSB at MMUv2 bank 0 (256 banks * 64k = 16MB) $D50D 1 MMUPG1L RAM bank LSB at MMUv2 bank 1 (256 banks * 64k = 16MB) $D50E 1 MMUPG2L RAM bank LSB at MMUv2 bank 2 (256 banks * 64k = 16MB) $D50F 1 MMUPG3L RAM bank LSB at MMUv2 bank 3 (256 banks * 64k = 16MB) $D510 1 MMUPG0H RAM bank MSB at MMUv2 bank 0 (65536 banks * 64k = 4GB) $D511 1 MMUPG1H RAM bank MSB at MMUv2 bank 1 (65536 banks * 64k = 4GB) $D512 1 MMUPG2H RAM bank MSB at MMUv2 bank 2 (65536 banks * 64k = 4GB) $D513 1 MMUPG3H RAM bank MSB at MMUv2 bank 3 (65536 banks * 64k = 4GB) $D600 1 VDCREG C128DX "Murrimi" VIX VDC -- C128 VDC compatible register access $D601 1 VDCDAT C128DX "Murrimi" VIX VDC -- C128 VDC compatible data register