Fox832 for Minimig MiSTer specs and memory map > MiSTer requirements * DE10 MiSTer FPGA * 32mb/64mb/128mb SDRAM expansion (used as Chip RAM) * Up to 256mb Fast RAM * 4gb potential addressing space > MiSTer recommended * I/O 5.5-6.0 board (any type) > MiSTer optional * USB Hub 1.1 (or 2.0) >> Specifications: > CPU K65832: Base: https://github.com/robfinch/Cores/tree/master/FT816 - With enhancements Enhanced implementation of WDC 65832 CPU (6502/65816 compatible) * Built in context switching for multitasking * Real, unmultiplexed 32 bit address/data buses with 4 byte selects * Speed: 66mhz (133mhz SDRAM / 2) operation * Extended addressing modes for 32bit access * Programmable Bank Mapper * Full Memory Management/Protection Unit * Extended instruction set (42xx) * Second status register * Unused opcodes on 6502 always map to new 16/32 instructions. > Video Interface Extended (VIX) * Up to 1280x720, 16M colors, 8bit alpha * CLUT / Planar / Chunky modes * Up to 256 sprites * Programmable raster interrupt * Scanline begin interrupt * Video modes for 16/24 bit addressing modes > Audio (SID Extreme) * 9x SID Extreme voices * Usual ADSR and Sawtooth/Pulse/Triangle/Noise waveforms * Additional 8/16 bit audio sample modes * 2 recording channels (left/right) * 65280 bytes dedicated SID Ex RAM for recording and SID playback >> Memory Map (Overview) Contents Addresses Size Type Description ----------------------------------------------------------------------------[All modes]- CPU RAM $0000FF00-$0000FFFF 256 SRAM Mirror of $FFFFFF00-$FFFFFFFF CPU RAM * $FFFF0000-$FFFFFFFF 64K SRAM CPU control RAM CPU RAM $FFFFFF00-$FFFFFFFF 256 SRAM 8/16/32 mode vectors and bootstrap (copied from ROM) ----------------------------------------------------------------------------[6502 mode]- LOW RAM $00000000-$00007FFF 32K SRAM TPA: 6502 mode chip RAM | Total 8bit *BANK RAM $00008000-$0000BFFF 16K ANY TPA: 6502 mode banked RAM 16x 1K banks | TPA: 32-48KB *BANK ROM $00008000-$0000BFFF 16K ANY 6502 mode BASIC or other languages BANK RAM $0000C000-$0000EFFF 12K CHIP FB:8 - 6502 mode framebuffer IO AREA $0000F000-$0000F7FF 2K IO 6502 mode banked IO area ROM $0000F800-$0000FFEF 2032 ROM 6502 "Kernel" (16 bit mode retpolines) ----------------------------------------------------------------------------[65816 mode]- LOW RAM $00000000-$0000FFEF 65280 SRAM 65816 Direct Page MID RAM $00010000-$0001FFFF 64K SRAM 65816 Stack Page MID RAM $00020000-$0002FFFF 64K SRAM 65816 Fast routine application area MID RAM $00030000-$0003FFFF 64K CHIP Clipboard (All modes) MID RAM $00040000-$00BFFFFF 12032K CHIP 65816 applications / data BANK RAM $00C00000-$00CFFFFF 1MB ANY 65816 banked RAM area (16x64k banks) BANK RAM $00D00000-$00DFFFFF 1MB CHIP FB:16 - 65816 video framebuffer IO AREA $00E00000-$00EFFFFF 1MB IO IO device and expansions ROM $00F00000-$00FFFFFF 1MB ROM 65816 ROMs ----------------------------------------------------------------------------[65832 mode]- UPPER RAM $01000000-$017FFFFF 8MB CHIP FB:32 - 65x832 mode framebuffer UPPER RAM $01800000-$01FFFFFF 8MB CHIP 65832 applications / data UPPER RAM $02000000-$1FFFFFFF 496MB CHIP CHIP RAM (expansion up to 512MB), 32 bit programs *HIGH RAM $20000000-$9FFFFFFF 2GB DDR3 HIGH RAM (Up to 2GB), 32 bit programs *HIGH IO $A0000000-$DFFFFFFF 1GB IO/DDR3 Expansion (MiSTer ARM retpoline) or DDR3 RAM *VIRT MEM $20000000-$DFFFFFFF 3GB MMU RAM alloc bottom up, IO alloc top down, unmapped = virtual memory HIGH IO $E0000000-$EFFFFFFF 256MB PCI PCI and PCI-e expansions HIGH ROM $F0000000-$FEFFFFFF 240MB ROM Expansion ROMs, 32 bit OSes HIGH ROM $FF000000-$FFFEFFFF 16128K ROM 32 bit Kickstart, Kernel, BIOS and GUI CPU RAM $FFFF0000-$FFFFFFFF 64K SRAM CPU RAM (see CPU spec) ----------------------------------------------------------------------------- * = Shared; CHIP = SDRAM; ANY = Any RAM type permitted, DDR3 = Expansion RAM or FPGA Native CPU RAM: SRAM or FPGA BRAM, accessible any time. CHIP RAM: Must be readable or writable on a per cycle basis. DDR3 RAM: Can wait for multiple cycles, should be accessed 32 bits at a time. >>>> LOW RAM: 16 bit addressing space $0000-$FFFF << Begin End/Len Desc/Usage ------- ------- ------------------------------------------------------------- $0000 512 Reserved for 6502 emulation mode (Zero page, Stack) $0200 512 8<->16<->32 bit mode retpoline vectors $0400 512 User application wedge vectors $0600 512 Reserved for OS use (BIOS, OS, Editor) $0800 512 Reserved for driver use (Sound, USB, Video, Text mode, Disk) $0A00 512 Reserved for module use (Network, IP, Filesystems) $0C00 512 Reserved for programming language (Lua, Forth, BASIC) $0E00 512 Usable by applications. >> 16/32 bit mode: 65816/65832 Direct Page: $000000-$00FFFF $0000 65280 Usable by user applications, 16/32 bit BASIC ----------------------------------------------------------------------------- >> 8 bit mode: 6502 Emulation address space $1000 28K Usable by user applications (Data area / 8 bit BASIC RAM) $8000 16K Banked RAM and ROM: Pointers to 24 bit address space by MMU registers at $F300-$F37F (bits 23-8) # NOTE: BASIC and other ROM applications will know how to use the banked RAM # for near unlimited program and variable capacity. >> 8 bit mode Framebuffer: (6502 framebuffer / Text screen area) > Text8 $C000 4096 6502 emulation text mode buffer char (4096 chars, 80x50) $C000 1*4K (ASCII character) $D000 4096 6502 emulation text mode buffer color (4096 chars, 80x50) $D000 1*4K (Color selector 0..255) $E000 4096 6502 emulation text mode buffer attrs (4096 chars, 80x50) $E000 1*4K (Attribute) 7: Bold 6: Underline 5: Italics 4: Blink 3-0: Charset number (Up to 16 ASCII fonts on screen) > Graphics-mono:8 $C000 12K 6502 graphics (12288 pixels) Fixed 320x240 or 400x240 > Graphics-4bit:8 $C000 12K 6502 graphics (12288 pixels) Fixed 160x120 or 200x120 > I/O AREA: # Examples: # Change entire 16K bank at $8000 to point at $01000000 (in chip): LDA.l #$0100008F: STA.l $F000 # Change entire 12K framebuffer at $C000 to point at $01200000 (in chip): LDA.l #$01200087: STA.l $F004 # Change $8000 and $9000 to point at the same RAM at $02000000: LDA.l #$02000030: STA.l $F000 # Yes, this means insanely fast page flipping. == Page Flipper == $F000 2 All Banks (16k) at $8000-$CFFF pointed at $nnxxxx00 (write triggers page flip) $F002 1 Must be specified first if being set, $nn for flipper at $F000 $F003 1 Must be set first if being set, number of 256 byte pages to flip (bits 0-5 valid) $F004 2 All Banks (12k) at $C000-$EFFF pointed at $nnxxxx00 (write triggers page flip) $F006 1 Must be specified first if being set, $nn for flipper at $F004 $F007 1 Must be set first if being set, number of 256 byte pages to flip (bits 0-5 valid) == IO Page Banker == == DMAgic32 - 8 bit mode registers === $F000 256 Mirror of $EC0000-$EC00FF $F100 256 I/O Mirror: $E001xx (VIX primary registers) $F200 256 I/O Mirror, $E100xx (SID Extreme) $F300 128 8 bit mode MMU, 64 entries: $F300 2 Bits 23-8 of address mapped at $80xx $F302 2 Bits 23-8 of address mapped at $81xx ... $F37E 2 Bits 23-8 of address mapped at $BFxx $F380 128 ROM Kernel scratch RAM $F400 3K ROM "kernel" (mostly a trampoline to 16 bit kernel) and processor init. $FFF0 16 ROM kernel vectors >>>>> MID RAM (SRAM): Data area (65816) $010000 64K 65816/65x832 Stack page $020000*64K $020000 32K Application area: Speed critical routines $028000 8192 Data area: User applications $02A000 4096 Data area: Data sharing $02B000 4096 Data area: OS $02C000 4096 Data area: Driver $02D000 4096 Data area: Modules $02E000 4096 Data area: Multi-user FORTH / BASIC $02F000 4096 Data area: GUI >>>>> MID RAM (CHIP): Data area (65816) $030000 64K Clipboard >> End data area >> User RAM (65816) $040000 $BFFFFF 12032K 65816 applications >> End user RAM >> Bank switched area (BSA) $C00000 1MB Memory banked area $C00000 64K Banked memory page 0 $C10000 64K Banked memory page 1 $C20000 64K Banked memory page 2 $C30000 64K Banked memory page 3 $C40000 64K Banked memory page 4 $C50000 64K Banked memory page 5 $C60000 64K Banked memory page 6 $C70000 64K Banked memory page 7 $C80000 64K Banked memory page 8 $C90000 64K Banked memory page 9 $CA0000 64K Banked memory page 10 $CB0000 64K Banked memory page 11 $CC0000 64K Banked memory page 12 $CD0000 64K Banked memory page 13 $CE0000 64K Banked memory page 14 $CF0000 64K Banked memory page 15 >> End BSA >> Framebuffer:16 $D00000 1MB Video frame buffer (See modes below) > Chunky Mode $D00000 1MB (921600 pixels RGBI2321) Max (960x720 | 1280x720) $D00000 1MB (921600 pixels CLUT) Max (960x720 | 1280x720) $D00000 1MB (480000 pixels RGBI5551) Max (800x600 | 800x480) $D00000 1MB (480000 pixels RGB565) Max (800x600 | 800x480) $D00000 1MB (480000 pixels RGB565) Max (800x600 | 800x480) $D00000 1MB (348160 pixels RGB888) Max (640x480 | 720x400 | 720*480 no text mode ) > Planar mode $D00000 340K (348160 pixels RED plane) Max (640x480 | 720x400 | 720x480 w/o text mode) $D55000 340K (348160 pixels GREEN plane) Max (640x480 | 720x400 | 720x480 w/o text mode) $DAA000 340K (348160 pixels BLUE plane) Max (640x480 | 720x400 | 720x480 w/o text mode) > Text mode $DF0000 64K Text mode buffer (placed here to be out of the way of graphics mode / allow split mode) $DF0000 16K Text mode chars (Up to 16384 characters on screen (160x90 max text resolution)) $DF0000 1*16K (ASCII char) $DF4000 16K Text mode attrs $DF4000 1*16K (Attribute) 7: Bold 6: Underline 5: Italics 4: Blink 3-0: Charset number (Up to 16 ASCII fonts on screen) $DF8000 32K Text mode color (up to 16384*16bit color) $DF8000 1*16K (8 bit CLUT) $DF8000 1*16K (8 bit RGBI2321) $DF8000 2*16K (16 bit RGBI5551) $DF8000 2*16K (16 bit RGB565) >> End video frame buffer >> IO Area $E00000 1MB I/O area (Device and expansion card access) >> System / Onboard devices $E00000 64k Onboard devices > MMU $E00000 256 Bank switching / MMU (Bank select is 16 bit and in this FPGA can select bank 0000 to 01ff (512 64k pages) but COULD access up to 4GB) $E00000 2 Select contiguous region for BSA $Cxxxxx (writing 0180 here would set banks 0..F to 0180..018F) $E00002 2 Select contiguous region for video framebuffer $Dxxxxx $E00004 2 Select contiguous region for ROM $Fxxxxx $E00006 2 MMU config 15-14: 00: Write protect violations ignored 01: WP violation triggers NMI 10: WP violation triggers IRQ 11: WP violation jumps to vector $E00008 2 Select contiguous region for PCM buffer $E0000A 2 Select number of pages of PCM buffer $E0000C 2 Select contiguous region for Sprite buffer $E0000E 2 Select number of pages of Sprite buffer $E0001x $E0001x Page write protect $xn0000 7-0: Write protect 8k*n (bitfield) $E00020 $E0003F Select page number for BSA page 0..15 $E00040 $E0005F Select page number for video framebuffer page 0..15 $E00060 $E0007F Select page number for ROM page 0..15 $E00080 $E000BF Reserved for more cool MMU stuff $E000C0 $E000FF RAM for WP violation routine (should prep stack and jump elsewhere) > Video >> $E00100-$E001FF default mapped to $F100-F1FF $E00100 1 Video mode - Primary (modetype:framebuffer it uses) - Starts at scanline 0 0: Off 8: Text:8 10: 4bit:8 (160/200)x120 only 16: Text:16 17: Mono:16 18: 4r:16 20: Framebuffer:16 32: Framebuffer:32 Bit 7: 0=4:3; 1=16:9 $E00101 1 Color mode - Primary 0: Off 8: FB:8 - CLUT1 Mono 9: FB:8 - CLUT2 4 color 10: FB:8 - CLUT4 16 color 16: FB:16 - CLUT1 Mono 17: FB:16 - CLUT2 4 color 18: FB:16 - CLUT4 16 coolor 19: FB:16 - CLUT8 256 color 20: FB:16 - Chunky RGBA2321 21: FB:16 - Chunky RGBA5551 22: FB:16 - Chunky RGB565 23: FB:16 - Chunky RGB6666 24: FB:16 - Planar R8G8B8 32: FB:32 - CLUT1 Mono 33: FB:32 - CLUT2 4 color 34: FB:32 - CLUT4 16 coolor 35: FB:32 - CLUT8 256 color 36: FB:32 - Chunky RGBA2321 37: FB:32 - Chunky RGBA5551 38: FB:32 - Chunky RGB565 39: FB:32 - Chunky RGB6666 40: FB:32 - Planar R8G8B8 41: FB:32 - Chunky RGBA8888 42: FB:32 - Planar R8G8B8A8 $E00102 1 Video mode - Split, as above - starts at scanline ($E00116) $E00103 1 Color mode - Split, as above $E00104 4 Video size H (Pixels) - Auto rounded up to next valid resolution $E00106 2 Video size V (Pixels) - Auto rounded up to next valid resolution $E00108 2 Video framebuffer size X - Can be anything that fits into 1MB memory $E0010A 2 Video framebuffer size Y - Can be anything that fits into 1MB memory $E0010C 2 Video framebuffer X position start (Offset of X that starts the display) $E0010E 2 Video framebuffer Y position start (Offset of X that starts the display) $E00110 1 Layer of framebuffer (0..255) Default 128 $E00116 2 Scanline # to start split screen mode at $E00118 2 Raster interrupt #0 scanline # $E0011A 2 Raster interrupt #1 scanline # $E0011C 2 Raster interrupt #2 scanline # $E0011E 2 Raster interrupt #3 scanline # $E0E000 256*4 CLUT palette (RGBA) 32 bit - Framebuffer $E0F000 256*4 CLUT palette (RGBA) 32 bit - Sprites $E01000 256*16 Sprite information Bytes 16-12: 32 bit address in RAM pointing directly at start of the sprite (sprites outside of chip RAM may not work we'll see, but if they do, cool) Byte 11: X size Byte 10: Y size Byte 9 : Layer (0-255) Byte 8 : Flags 7-6: Size multiplier+1 (Byte11,Byte10)*((Bits 7-6)+1)=Actual size NOT the same as scale. 256x256 + 0x3 here = a 1024x1024 sprite and the data must be provided at the given address. 5-4: Color type: 00=CLUT (0 not used) 01=RGBA2321 10=RGBA5551 11=RGBA6666 3-1: Reserved 0: Freeze sprite (1=do not reflect changes being made, 0=Reflect changes being made) Byte 7 : 7-6: 00: No rotation 01: 90 degree rotation 10: 180 degree rotation 11: 270 degree rotation 5: 1: Flip X 4: 1: Flip Y Byte 6 : Scale (0=off, 1=1/16x, 16=1x, 255=~16x) Byte 5 : Direction (pi/256) Byte 4 : Speed (pixels/sec) Byte 3-2 : X position Byte 1-0 : Y position $E0FF00 240 VERA emulation: See VERA docs for register docs $E0FFF0 16 VERA emulation: Exposed VERA registers (as on x16) > Sound! Wait till you see this... >> $E10000-$E100FF default mapped to $F200-$F2FF for 8 bit use. -- SID Extreme 16581 device -- $E10000 64K SID Extreme 16581 device $E10000 256 SID Extreme sound registers $E10100 65280 SID Extreme Dedicated RAM $E10000 32 **** SID 6581/8580 register map emulation (center channel) $E10000 7 Voice 1 (center) (ring/modulate with voice 3) $E10007 7 Voice 2 (center) (ring/modulate with voice 1) $E1000E 7 Voice 3 (center) (ring/modulate with voice 2) $E10015 2 Filter cutoff frequency $E10017 1 Filter resonance and routing 7-4: Resonance 3: External input 2: Voice 3 1: Voice 2 0: Voice 1 $E10018 1 Filter mode and volume 7: Mute voice 3 6: High pass 5: Band pass 4: Low pass 3-0: Legacy volume control (New volume high nybble mirror) $E10019 1 Voice 1 oscillator $E1001A 1 Voice 1 envelope $E1001B 1 Voice 3 oscillator $E1001C 1 Voice 3 envelope $E1001D 1 Voice 2 oscillator $E1001E 1 Voice 2 envelope $E1001F 1 New 8 bit volume control (high nybble mirrored in $E10018) $E10020 32 **** SID 6581/8580 register map emulation (SID 2 Left [AS ABOVE except +$20]) $E10020 7 Voice 4 (left) (ring/modulate with voice 6) $E10027 7 Voice 5 (left) (ring/modulate with voice 4) $E1002E 7 Voice 6 (left) (ring/modulate with voice 5) $E10035 2 Filter cutoff frequency $E10037 1 Filter resonance and routing 7-4: Resonance 3: External input 2: Voice 6 1: Voice 5 0: Voice 4 $E10038 1 Filter mode and volume 7: Mute voice 6 6: High pass 5: Band pass 4: Low pass 3-0: Legacy volume control (New volume high nybble mirror) $E10039 1 Voice 4 oscillator $E1003A 1 Voice 4 envelope $E1003B 1 Voice 6 oscillator $E1003C 1 Voice 6 envelope $E1003D 1 Voice 5 oscillator $E1003E 1 Voice 5 envelope $E1003F 1 New 8 bit volume control (high nybble mirrored in $E10038) $E10040 32 **** SID 6581/8580 register map emulation (SID 3 Left [AS ABOVE except +$40]) $E10040 7 Voice 7 (left) (ring/modulate with voice 9) $E10047 7 Voice 8 (left) (ring/modulate with voice 7) $E1004E 7 Voice 9 (left) (ring/modulate with voice 8) $E10055 2 Filter cutoff frequency $E10057 1 Filter resonance and routing 7-4: Resonance 3: External input 2: Voice 9 1: Voice 8 0: Voice 7 $E10058 1 Filter mode and volume 7: Mute voice 9 6: High pass 5: Band pass 4: Low pass 3-0: Legacy volume control (New volume high nybble mirror) $E10059 1 Voice 7 oscillator $E1005A 1 Voice 7 envelope $E1005B 1 Voice 9 oscillator $E1005C 1 Voice 9 envelope $E1005D 1 Voice 8 oscillator $E1005E 1 Voice 8 envelope $E1005F 1 New 8 bit volume control (high nybble mirrored in $E10058) $E10060 32 **** SID Extreme Control Registers $E10060 16 **** SID Extreme recording registers (Addresses that are 16bit point into SID Extreme RAM) $E10060 1 SID Extreme recording control register 7: 1: Record 16 bit samples 0: Record 8 bit samples 5: 1: Enable left channel recording; 0: Disable 4: 1: Enable right channel recording; 0: Disable 3: 1: Enable left channel recording passthrough (to left output); 0: Disable 2: 1: Enable right channel recording passthrough (to right output); 0: Disable $E10062 2 SID recording buffer sample rate (left/right) $E10064 2 SID recording buffer left channel capture pointer $E10066 2 SID recording buffer right channel capture pointer $E10068 2 SID recording buffer left channel start pointer $E1006A 2 SID recording buffer left channel ring length $E1006C 2 SID recording buffer right channel pointer $E1006E 2 SID recording buffer right channel ring length $E10070 16 SID Extreme Voice 1 (default both channel) $E10080 16 SID Extreme Voice 2 (default both channel) $E10090 16 SID Extreme Voice 3 (default both channel) $E100A0 16 SID Extreme Voice 4 (default left channel) $E100B0 16 SID Extreme Voice 5 (default left channel) $E100C0 16 SID Extreme Voice 6 (default left channel) $E100D0 16 SID Extreme Voice 7 (default right channel) $E100E0 16 SID Extreme Voice 8 (default right channel) $E100F0 16 SID Extreme Voice 9 (default right channel) > Voice registers + $00 2 Voice frequency (for RAW samples should be set equal to 02 UNLESS intentionally pitch skewing) + $02 2 Voice pulse wave duty cycle (pulse waveform) OR + $02 2 Voice RAW base frequency (Frequency that wave sample was encoded at) + $04 1 Voice control register 7: Noise 6: Pulse 5: Sawtooth 4: Triangle 3: RAW 2: Modulate 1: Synchronize 0: Gate + $05 1 7-4: Attack 3-0: Decay + $06 1 7-4: Sustain 3-0: Release > Voice extended registers (present at voice registers above $E10040, not in 6581 space $E10000-$E1003F) + $07 1 Voice extended control register 7: 0: RAW one shot (Play sample once then stop) 1: RAW continuous (Repeat sample) 6: 0: 6581 filtering 1: 8580 filtering 3: Voice bitness (0:8 bit, 1:16 bit) 1: Continuation register: 0: Changes to $08-0C take place immediately. 1: Changes to $08-0C take place when current sample finishes (use to play more than 64kb samples) 0: 0: Immediately terminate playback of sample 1: Start playback of sample from beginning + $08 3 Location in Chip RAM of RAW sample (Could be in SID dedicated RAM) + $0B 2 Length of sample (up to 64kb) + $0D 1 Volume adjustment of left channel (00=mute, FF=full) + $0E 1 Volume adjustment of right channel (00=mute, FF=full) + $0F 1 Voice extended control register 2 7: Mute, terminate, and reset channel to defaults 6: 1: Retrieve sample information before playback: Bytes 00-01 to register 02 (Sample frequency) Bytes 02-03 to register 0B (Sample length) Byte 04 bit 0 to register 07 bit 3 (Sample bitness) If Byte 04 bit 7 set: (For more information) Byte 04 bit 1 to byte 07 bit 7 (Set whether one shot or continuous) Byte 05 to register 0D (Set left default volume) Byte 06 to register 0E (Set right default volume) If Byte 04 bit 6 set: Byte 07-08 to reg 00-01 (Sets target frequency) Else: Reg 02-03 cloned to 00-01 (sets base and target frequency the same [no pitch change]) If Byte 04 bit 0 set: Playback started at byte 0A (byte 09 reserved and ignored) Else: Playback will start at byte 0A when triggered ($07 bit 0) 0: Do not retrieve sample information, assumed manually set, playback will begin at byte 00 3-0: Voice that Modulate/Synchronize operates with $EC0000 === MMU And DMAgic32 === $EC0008 2 Pointer to mirror of IO registers $F400 ($0000 at boot) (Unmapped) $EC000A 2 Pointer to mirror of IO registers $F500 ($0000 at boot) (Unmapped) $EC000C 2 Pointer to mirror of IO registers $F600 ($0000 at boot) (Unmapped) $EC000E 2 Pointer to mirror of IO registers $F700 ($0000 at boot) (Unmapped) $EC0010 4 32bit source address $EC0014 4 32bit destination address+ $EC0018 4 32bit payload length $EC001C 1 Operation (done msb-lsb order) 7-6: Unit size in bits (00=4bit; 01=8bit; 10=16bit; 11=32bit) 5: AND source with destination 4: OR source with destination 3: XOR source with destination 2: ADD source to destination 1: SUBtract source from destination 0: Treat source as zeroes (init destination) $EC001D 1 Operation trigger 7: Copy source to destination 6: Copy destination to source 5: Swap destination and source 4: Copy source to only destination address ($Payload times) 3: Wait for NMI to perform transfer 2: Synchronize transfer with a timer 1: Switch endian during transfer 0: One shot: Perform one unit transfer and wait for next shot to do next transfer >> Emulated devices (RAM, but sets off interrupts when accessed outside of an interrupt) $EC8000 4096 Emulated device 0 $EC9000 4096 Emulated device 1 $ECA000 4096 Emulated device 2 $ECB000 4096 Emulated device 3 $ECC000 4096 Emulated device 4 $ECD000 4096 Emulated device 5 $ECE000 4096 Emulated device 6 $ECF000 4096 Emulated device 7 (Reserved for simulating C64 $Dxxx [with VERA at $ECF700] or Apple $Cxxx IO) >> Block devices (HD/CD/Flash/VHD) $ED0000 64K Block device control area $ED0000 4096 Block device 0 $ED1000 4096 Block device 1 $ED2000 4096 Block device 2 $ED3000 4096 Block device 3 $ED4000 4096 Block device 4 $ED5000 4096 Block device 5 $ED6000 4096 Block device 6 $ED7000 4096 Block device 7 $ED8000 4096 Block device 8 $ED9000 4096 Block device 9 $EDA000 4096 Block device 10 $EDB000 4096 Block device 11 $EDC000 4096 Block device 12 $EDD000 4096 Block device 13 $EDE000 4096 Block device 14 $EDF000 4096 Block device 15 > Block device registers + $00 1 Block device control register 7: 0=trigger read; 1=trigger write 6: 1=TRIM sector (if SSD) 5: Read/write count (up to 64 sectors) + $01 1 Block device status register 7: Write protect 6: Read/write complete + $02 4 Block device size (in 'sector size' units) + $06 2 Sector size (bytes) (Support up to 256TB block device at 64K sector size) + $08 248 Select tracls + $100 256 Sector buffer 1 + $200 256 Sector buffer 2 + $300 256 Sector buffer 3 + $400 256 Sector buffer 4 + $500 256 Sector buffer 5 + $600 256 Sector buffer 6 + $700 256 Sector buffer 7 + $800 256 Sector buffer 8 + $900 256 Sector buffer 9 + $A00 256 Sector buffer 10 + $B00 256 Sector buffer 11 + $C00 256 Sector buffer 12 + $D00 256 Sector buffer 13 + $E00 256 Sector buffer 14 + $F00 256 Sector buffer 15 > Virtual block devices (by file access) $EE8000 4096 Virtual block device 0 $EE9000 4096 Virtual block device 1 > Floppies (as per registers) $EEA000 4096 Floppy 0 $EEB000 4096 Floppy 1 $EEC000 4096 Floppy 2 $EED000 4096 Floppy 3 > Floppy device registers + $00 1 Floppy control register 7: 0=trigger read; 1=trigger write 6-4: Read/write count (1-8 sectors) 3-0: Pointer to 256 byte sector buffer at +$x00 + $01 1 Floppy status register 7: Write protect 6: Read/write complete + $02 1 Select sector 7: Head (0/1) 6-0: Sector (0-127) + $03 1 Select Track (0-255) + $04 1 Maximum detected sector usually $A4 (2 heads 36 256 byte sectors) 7: Head (0/1) 6-0: Sector (0-127) + $05 1 Maximum detected Track (0-255) usually $50 (80 tracks) + $06 1 Sector size (256*x) + $07 1 Seek to and format track (0-255) + $08 248 Reserved + $100 256 Sector buffer 1 + $200 256 Sector buffer 2 + $300 256 Sector buffer 3 + $400 256 Sector buffer 4 + $500 256 Sector buffer 5 + $600 256 Sector buffer 6 + $700 256 Sector buffer 7 + $800 256 Sector buffer 8 + $900 256 Sector buffer 9 + $A00 256 Sector buffer 10 + $B00 256 Sector buffer 11 + $C00 256 Sector buffer 12 + $D00 256 Sector buffer 13 + $E00 256 Sector buffer 14 + $F00 256 Sector buffer 15 > Autoconfig Expansion Area / Future planned expansions $EEE000 256 Reserved $EEE100 256 Apple II compatible expansion slot 1 (Printer) $EEE200 256 Apple II compatible expansion slot 2 (Modem) $EEE300 256 Apple II compatible expansion slot 3 (80 Col / RAM) $EEE400 256 Apple II compatible expansion slot 4 () $EEE500 256 Apple II compatible expansion slot 5 (Floppy) $EEE600 256 Apple II compatible expansion slot 6 (Floppy) $EEE700 256 Apple II compatible expansion slot 7 (Hard disk) $EEE800 16*16 SPI access $EEE900 256 Reserved $EEEA00 256 Amiga compatible Autoconfig Expansion Area (Zorro II/III card - relocated to $Axxxxxxx-$Dxxxxxxx in reverse) $EEEB00 256 C64 compatible expansion (Device 1) $EEEC00 256 C64 compatible expansion (Device 2) $EEED00 256 C64 compatible expansion (Device 3) $EEEE00 16 Autoconfig Expansion Area (16 bytes registers) $EEEF00 256 Autoconfig area 256 byte communication buffer (pre-configuration) $EEF000 4096 256*16 List of configured devices (16 bytes registers) > Autoconfig Expansion Registers (16 bytes) + $00 1 (W) Request Expansion # (00=request any unconfigured expansion) + $01 1 (R) Expansion type 7-4: Bus type: 0: Device not present 1: SPI 2: GPIO 3: I2C 4: USB 8: HPS A: Apple II expansion C: Zorro D: PCI E: PCI-e F: Memory 3-0: Device base type: 0: Device not present 1: Serial device (Transfers one bit at a time) 2: Parallel device (Transfers >1 bit at a time) 4: Block device (Does buffer transfers [floppy, HD, CD]) 8: Network device (Does buffer transfers) F: RAM device (Maps to a memory address) + $02 1 Expansion subtype (Will be assigned) + $03 1 Expansion capabilities (Will be assigned) + $04 2 Page to move expansion to (256 byte page boundary in lower 16M) (Almost always this will be somewhere in $Exxx) (If expansion is of type FF [Memory] will be moved to $xxxx0000) + $06 2 Size of expansion (in 256 byte page size, 04 = 1024 bytes) (Minimum size of an expansion is 256 bytes) + $08 1 Expansion status 7: 0 = unconfigured; 1 = configured 6: 1 = trigger leave bus and power off 5: 1 = trigger power on and reconfigure (at $EEEE00) 4: 1 = trigger power on and don't configure 0: 1 = trigger final configuration (and move to new address) + $0A 2 PCI/USB/Zorro/Etc: Device vendor word + $0C 2 PCI/USB/Zorro/Etc: Device product word + $0E 2 PCI/USB/Zorro/Etc: Device version word >> Interrupt handling $EFF000 $EFFFFF Programmable Interrupt Controller $EFF000 4*256 256 programmable interrupt handlers + $00 7: 1 = Interrupt triggered 6: 1 = Interrupt disabled 5: 1 = Automatically disable interrupt on trigger 4-3: Interrupt priority: 0 highest; 3: Lowest 2: 1 = Disable all lower priority interrupts on interrupt 0 = Reenable all lower priority interrupts on bit write (writing 0 then 1 to this bit will reenable lower priority interrupts then set to disable them again on next interrupt) 1-0: 00 = Do not handle interrupt 01 = Handle as a 6502 interrupt (jump to 8 bit IRQ vector) 10 = Handle as a 65816 interrupt (jump to 16 bit irq vector) 11 = Jump to set vector on interrupt + $01 3 Chip ram address of interrupt handling routine $EFF000 4 IRQ 00: NMI $EFF004 4 IRQ 01: Task Scheduler $EFF008 4 IRQ 02: Reserved $EFF00C 4 IRQ 03: Reserved $EFF010 4 IRQ 04: Raster interrupt (Every line) $EFF014 4 IRQ 05: Reserved $EFF018 4 IRQ 06: HPET 0 $EFF01C 4 IRQ 07: HPET 1 $EFF020 4 IRQ 08: Raster interrupt programmable 0 $EFF024 4 IRQ 09: Raster interrupt programmable 1 $EFF028 4 IRQ 0A: Raster interrupt programmable 2 $EFF02C 4 IRQ 0B: Raster interrupt programmable 3 $EFF100 4 IRQ 40: CPU Exception (General) $EFF104 4 IRQ 41: CPU Exception (Division by zero) $EFF108 4 IRQ 42: CPU Exception (NaN exception) $EFF10C 4 IRQ 43: CPU Exception (Undefined opcode) $EFF140 4 IRQ 50: MMU: Parity/Corruption $EFF144 4 IRQ 51: MMU: No RAM present at address $EFF148 4 IRQ 52: MMU: Attempted write of WP mem / ROM $EFF14C 4 IRQ 53: MMU: Attempted read of read protected page $EFF150 4 IRQ 58: MMU: Access of emulated device 0 ($EC8xxx) $EFF150 4 IRQ 59: MMU: Access of emulated device 1 ($EC9xxx) $EFF150 4 IRQ 5A: MMU: Access of emulated device 2 ($ECAxxx) $EFF150 4 IRQ 5B: MMU: Access of emulated device 3 ($ECBxxx) $EFF150 4 IRQ 5C: MMU: Access of emulated device 4 ($ECCxxx) $EFF150 4 IRQ 5D: MMU: Access of emulated device 5 ($ECDxxx) $EFF150 4 IRQ 5E: MMU: Access of emulated device 6 ($ECExxx) $EFF150 4 IRQ 5F: MMU: Access of emulated device 7 ($ECFxxx) $F00000*$FFFFFF 1MB ROM: (Allocated in 256 4KB pages) $F00000 $F5FFFF 384K ROM: 16 bit GUI (Workbench16 / OpenGEM) $F60000 $F9FFFF 256K ROM: 16 bit Kernel $FA0000 $FA3FFF 16K ROM: Amiga Topaz font - Default font $FA4000 $FA7FFF 16K ROM: Macintosh 68K Font $FA8000 $FA87FF 2K ROM: Apple II font 256 8x8 $FA8800 $FA8FFF 2K ROM: NES font 256 8x8 $FA9000 $FA97FF 2K ROM: Atari ST font 8x8 $FA9800 $FA9FFF 2K ROM: VIC 20 font 256 8x8 PETSCII $FAA000 $FAA7FF 2K ROM: Commodore 8 bit font 256 8x8 ASCII $FAA800 $FAAFFF 2K ROM: Fox832 extended character font 256 (accented chars) $FAB000 $FAB7FF 2K ROM: Fox832 Window glyphs (for drawing GUI, ctrl chars) $FAB800 $FABFFF 2K ROM: Fox832 Animal glyphs (Unicode 9.0 animal set) $FAC000 $FADFFF 8K ROM: Commander x16 compatible BASIC extensions $FAE000 $FAFFFF 8K ROM: Commodore BASIC 2.0 $FB0000 $FBFFFF 64K ROM: 16/32 bit BASIC (BASIC 10.0 based) $FC0000 $FC3FFF 16K ROM: Full screen editor $FC4000 $FC7FFF 16K ROM: Sprite editor $FC8000 $FCBFFF 16K ROM: SID player/Composer $FCC000 $FCFFFF 16K ROM: 8/16/32 bit Machine language monitor / assembler $FD0000 $FDFFFF 64K ROM: DOS Filesystems (1541/71/81, FAT32, ExFat, Ext4, Amiga PFS) $FE0000 $FE7FFF 32K ROM: FORTH interpreter $FE8000 $FEFFFF 32K ROM: COMAL-80 interpreter $FF0000 $FFFFFF 64K CPU: Memory >> Upper RAM $01000000 * $017FFFFF 8MB Framebuffer:32 (Supporting very high res modes) MiSTer 32MB SDRAM module Up to 1920x1080 RGBA8888 or 3840x2160 RGBA2321 or CLUT $01800000 * $01FFFFFF 8MB 32 bit applications. 32MB is the minimum amount of chip! $02000000 * $1FFFFFFF 496MB RAM for user applications (if present) Future SDRAM expansions >> High RAM $20000000 * $9FFFFFFF 2GB High RAM (Long addressable) DE10 DDR3 memory $20000000 * $9FFFFFFF 2GB Virtual memory (unmapped) >> High IO $A0000000 * $DFFFFFFF 1GB Reserved for future use (Zorro II/III Expansion) $A0000000 * $DFFFFFFF 1GB Virtual memory (unmapped) $E0000000 $EFFFFFFF 256MB Reserved for future use (PCI) >> High ROM $F0000000 $FEFFFFFF 240MB ROM expansions and 32 bit OS $FF000000 $FFEFFFFF 15MB 32 bit Kickstart, Kernel, BIOS and GUI $FF000000 $FFFFFFFF 1MB 16 bit kernel (mirrored at $00F00000-$00FFFFFF)