------------------------------------------------------------------------------ > 65x832 Specs and Enhancements > https://public.kitsunet.net/832/W65C832%20CPU%20Datasheet%20v2.0.pdf > Based on the above W65C832 document. This file only documents changes. > This file may be modified at any time, even as you read it. ------------------------------------------------------------------------------ >>> Features Physical differences (Requirements for physical implementation or conversion to ASIC) * Completely compatible with 6502/65816 internally * 6510/8502 emulation mode pins. * Easy interfacing logic to replace a 6502/6510/8502/65816 (requires a CPU slot daughterboard) * 33mhz operation (initially). Expects to interface to 133mhz capable SDRAM. * DDR 1/2/3 RAM support (Maybe..) * 256K on die BRAM or SRAM * Tri-statable bus (If not connected to RAM at reset, it uses SRAM as RAM) * Internal RAM accessible by external devices. * Full 32 bit address and data bus, not multiplexed, 100 pins. * Byte enables for all 4 bytes on the data bus. * Coprocessor support. * I/O port support. * Slave mode and Multiprocessor support. * 16 internal high performance event timers. * Powerful register manipulation instructions. Never wonder where you're saving your registers again. * Powerful processor state manipulation instructions. Easily switch tasks and set up a multitasking system. * NOTE: Will not include undocumented 6502/6510 instructions, or later 65c02 bit instructions. >>> Pinout https://docs.google.com/spreadsheets/d/1eWHVqSCwqsYmfZpyUEyNvPEN1rrigfIV5PFKnY_wm3E Pin Descriptions (Including old pins) /RW (O) Read-Write (Hi: Read, Low: Write) Not a new pin but it should be noted that not only does this reflect the state of the data bus, but of the byte enable pins as well on this CPU. /ACT (O) Active Low when the processor is executing instructions. High under the following conditions: a) The processor has been stopped with STP b) The processor is waiting for an interrupt at a WAI instruction c) The processor is waiting for the bus to become available again (usually due to BE being pulled low without MP being pulled high, or MP is high but the next operation requires the system bus) d) The processor is waiting for the coprocessor to complete its transaction e) The processor is waiting for a port transaction to finish. f) The processor is waiting for a timer to alarm. ABM0-1 (I) Address Bus Mode Indicates what part of the address bus is valid and what should be forced to 00 00) 32 bit mode with external RAM (Normal) 01) 16 bit mode, all addresses are $0000-$FFFF. In 65816 mode, it acts like 65802 10) 24 bit mode, like 65816, all addresses are $000000-$FFFFFF. 11) Slave mode, an external device can access and change the CPU's RAM. BA (O) Bus Arbitration When BA is asserted, it means the CPU needs to be on the bus and will be halted until the bus is ocne again available. BE (I) Bus Enable Also AEC in 8502 mode, this places the CPU on and off the system bus. NOTE: Between BA and BE, full arbitration of the bus between devices can occur. BE0-3 (I/O) Byte enable 0-3 For the purposes of reading and writing to RAM, indicates which bytes on the data bus are valid and should be read or written. For the purposes of coprocessing, indicates the size of the operand. For the purposes of data port access, indicates the size of the payload. BREQ (I) Bus Request An input signal to indicate that an extenal device wants to transfer information to the CPU, usually in response to a Port or Coprocessor select, or a desire to send a named IRQ. See below for examples, but usually to assert the bus, bring BREQ high, wait till /ARW and /RW are asserted READ, then place your data on the address and data bus. Then deassert BREQ to indicate the data is ready. C= (I) 8502 emulation mode When driven high, memory addresses 0 and 1 respond like an 8502 would, and the status of P0-P7 is reflected at port address $FFFFFFFF (all address bus, and PS asserted) in D0-D7. An external chip can detect these conditions and select the pins required to interface to a C64 or 128. CPS (O) Coprocessor Select Allows an external coprocessor to be used. See Coprocessor interaction below. Instruction: 42 02 xx xx xx xx E (O) Emulation mode Reflects the value of the "E" flag in the processor status register. E32 (O) Extended 32bit Indicates the processor is running in 32 bit mode. /IRQ (I) Interrupt (Active low) Triggers an interrupt. MP (I) Multiprocessing Mode When asserted, this causes the following conditions to occur: 1) The CPU will be off bus whenever possible /ML (O) Memory Lock Indicates the need to defer arbitration of the next bus cycle. MX (O) Memory/Index Select Status Indicates the state of the MX flags. During phi2 positive, reflects the X flag, during phi2 negative, reflects the M flag. High=16 bit, low=8 bit MX32 (O) Memory/Index Select Status 32 Indicates the state of the MX32 flags. During phi2 positive, reflects the X flag, during phi2 negative, reflects the M flag. High=32 bit, low=MX is valid PHI2 (I) Phi 2 clock Input clock. By default, 33mhz is expected, but it could be any speed the CPU can handle. If it is a speed other than 33mhz, slave mode (ABM=11) should be asserted and the clock speed in cycles should be written to $FFFFF420, to ensure the accuracy of the timers. PHI0 (O) Phi 0 clock sync A potentially clock divided output clock sync. Its clock rate is the input clock divided by the rate set by the SPD (42 42 DB xx) instruction. This provides a second clock synced to a divisor of the clock driving the CPU. To produce the clock, AND this pin and the input clock. To drive a VIC for example, if the input clock is 33mhz, try SPD #$21. PS (O) Port Select When this is asserted, it signals to the external bus that the address/data bus has addresses meant for NOT memory mapped I/O devices. There can be 2^32 ports that take 32 bits of data. The difference between these devices and memory mapped devices are described below. RA (I) RAM Assertion This is used for a few different purposes: 1) An external MMU can assert it during normal operation to indicate that there was nothing addressable at the address requested. This will raise an interrupt and the system can respond as it likes to this interrupt (such as virtual memory) 2) When addressing a coprocessor, the coprocessor should assert this when it wants the CPU to modify a location in its own memory (noted on the address/data buses) SIG (O) Processor Signal Means different things at different times and is a generic way for the CPU to signal the outside world that something needs attention or an operation has completed. SPI (I) Special Processor Invocation Used to change the function of the return values placed on the bus by a coprocessor or device, or to invoke special bootstrap modes. >>> Bootstrapping methods * Different CPU start/reset methods can be invoked by holding certain lines in a state as indicated below. * To invoke any mode other than Legacy, the lines must be asserted while /RESET is asserted. * Boot sequence goes as follows: 1) The CPU will spend 4 cycles off the bus when powered on. a) You should spend these cycles setting the lines to get your desired mode. b) If /RESET is never driven low during power on, 2) If you are booting as a legacy 6502/65816, drive BREQ and SPI low. a) Else, drive the lines according to how it is specified below. >> Legacy (BREQ low, SPI low) * The system bootstraps as per the 6502/65816, in 8 bit mode. This is the default mode. * A minimum of 16 bytes of ROM/preinitialized RAM must be provided at $0000FFF0 to use this mode. * More should probably be provided to give the CPU something to boot. * This mode should be completely compatible with the 6502, 6510, 8502, 65802, and 65816. * It bootstraps to the 8 bit reset vector at $FFFC. >> Legacy Plus (BREQ low, SPI high) * As above, except the 256 bytes of ROM/preinitialized RAM are transferred to the CPU RAM before invoking this mode. * 256 bytes of ROM are required at $FF00-$FFFF * 176 bytes of this ROM area can be used to further bootstrap the system. * This mode can be very compatible with 6502/65816 boot modes. >> ROM to RAM preload bootstrap (BREQ high, SPI low) * The CPU transfers ROM to its own RAM before starting. * The CPU is started in 32 bit mode. * A 64K ROM is expected to be present in this mode, mapped at $FFFF0000-$FFFFFFFF (or otherwise have something on the bus there to read). * The entire contents of the ROM will be transferred to the CPU RAM area at $FFFF0000-$FFFFFFFF. * This can initialize vectors, the VEC instruction data area, and even the registers and stack. * This can ALSO be external RAM preinitialized with data, allowing an instant resume system to be implemented. * After the transfer is complete, the processor will start at the vector specified at $FFFFFFDC. >> ROM to RAM clean preload bootstrap (BREQ high, SPI high) * Similar to above. * When booted this way, the transfer above takes place, but then resets the entire CPU area from $FFFFC000 to $FFFFFEFF. 48KB of RAM and the 256b of bootstrap RAM and vectors are preserved. * Bootstrap then occurs as above. >> Direct load (BREQ/SPI as above, ABM0 and ABM1 high) * The CPU first starts up in one of the above modes. * The CPU then goes into slave mode. * Read the documentation below on how to use slave mode. * After the CPU is released from slave mode, the CPU will call the reset vector of its given mode. >> All boot modes * If /ABT is asserted at boot, it will not boot from the reset vector, but instead try to continue from the program counter. * Use this to do a hot continue of the system if desired, to change the CPU's modes without a full reset, or otherwise run a custom boot from a preloaded RAM system. NOTE: Preload and directload can be used at the same time (RA and BREQ held high). When this occurs, the preload bootstrap will occur first, then it will go to directload, allowing you to change the preloaded data. >>> Coprocessor operation (42 02 xx xx xx xx) When the COP instruction is executed, 1) The values on the address and data bus will be saved. 1) $xxxxxxxx will be placed on the address bus. 2) The accumulator will be placed on the data bus. 3) CPS will be brought high, and /RW will go high (WRITE). 4) The coprocessor should read the address bus for the instruction desired to be executed, and read the data bus for its argument. 5) Bring BREQ high to indicate the beginning of the coprocessor transaction, a) Keep BREQ asserted during the entire coprocessor operation. 6) If the coprocessor needs the system bus it can optionally pull BE (Bus enable) low. a) The processor will halt until BE is reasserted, you can also do DMA during this time. 7) The coprocessor should now perform its work. a) The bus should not be accessed until either /RW or /ARW go low (READ). b) Unless you have taken the CPU off the bus by deasserting BE. 8) Once done with the task, make sure either /RW or /ARW are low before writing to the bus. a) Assert BE if you were using the system bus to bring the CPU back. b) Assert RA if memory indicated at the address on the bus should be updated from the data bus. Note that 9) Assert any byte enables required (asserting none means no memory or registers will be modified) 10) Disassert BREQ to signal the processor you are done. 11) The 832 will respond according to the preceding pins indications, then continue processing. 12) It is possible for multiple coprocessors to exist. If using multiple coprocessors, I recommend the most signficant byte be used to indicate which processor to address. >>> Port operation Port operation works alot like memory bus-wise, with some exceptions. 1) All addresses are 32 bit, so $00000020 refers to a 32 bit port. $00000021 is entirely separate and does NOT get the second byte written at $00000020. 2) There are two instructions to interact with a port, INP and OUT. Its argument, the port #, is always 32 bit. 3) The size of the data bus (like memory) is indicated by the instruction. 4) For both INP and OUT, operation proceeds much like the coprocessor. a) It will place the port # on the address bus. b) For OUT, it will put the accumulator on the data bus. c) For INP, READ on /RW will be asserted. For OUT, WRITE on /RW will be asserted. d) It will assert PS (port select). 5) Assert BREQ to indicate the beginning of processing. 6) Perform your I/O operation. You can also use the bus (since the CPU is not on it) particularly if your I/O device is on the bus. 7) If this is an INP operation, set the data bus and the byte selects accordingly. 8) An IRQ can also be asserted as below. 9) When done, disassert BREQ. 10) If this was an INP operation, the value on the data bus will be loaded into the accumulator. a) Unless SPI is asserted, in which it will be sent to the Y register. 11) If RA is asserted, the memory location on the address bus will get the value on the data bus as well. >>> IRQ operation (New features) Any external device can send an IRQ and signal where it is coming from very easily. To use this feature: 1) Assert Bus Request (BREQ) and wait for /ARW to go low. 2) Set the address bus to the source of the IRQ. This can be any 32 bit integer. 3) Set the data bus to any data you want to send from the IRQ. 4) Assert the SPI line and the /IRQ or /NMI line. The SPI line here tells the CPU we are using a new style IRQ. Only /IRQ and /NMI can use a new style IRQ. 5) Assert (Bus enable). The registers will automatically be saved then the IRQ or NMI vector will be called with the address bus in Y and the data bus in A. >>> Vector ($02) instruction: NOTE: In order to maintain compatibility, The COP vector MUST be set to #$FFFF (or #$FFFFFFFF) for the given mode or the legacy behaviour of COP (calling the vector) will occur. NOTE: Also note that you can set it per mode, so you can have $02 act like COP in 16 bit mode (by setting the 16 bit vector to a valid address) while setting it to $FFFF in the 8 bit vector and $FFFFFFFF in the 32 bit vector to enable the use of vectors in those modes. NOTE: On reset, these vectors are set to $FFFF/$FFFFFFFF making the availability of VEC the default. * When the COP vector for the given COP instruction is set to all 1's ($FFFF/$FFFFFFFF), * COP will be replaced with the VEC instruction. The vector table will always live between $FFFFF000 and $FFFFF3FF (1024 bytes for 256*32bit vectors in CPU RAM). * The VEC instruction performs several steps above and beyond simply doing a jump to subroutine: 1) Does the equivalient of the "PHR T" to place the current processor state on the stack. 2) Decode the address of the destination vector, and decide what mode to go to: a) An address of 0000xxxx changes to 6502 mode. b) An address of 00xxxxxx changes to 65816 mode. c) An address of xxxxxxxx changes to 65832 mode. 3) Set the new processor mode. 4) Set the SV flag in the extended status register. a) ALL interrupts including NMI are ignored when SV is set, however when SV is unset the last NMI or IRQ that occured will be invoked as if RTV ended a CPU instruction. 5) Jump to the routine at the vectors address. 6) At this point it will execute the routine. The routine should return with the RTV instruction. 7) RTV will clear the SV flag and restore the processor state as per the "PLR T" instruction. 8) The previous function of COP can be accessed now invoked using $42 $02 $xx if VEC is enabled. a) The argument of the Legacy COP instruction is 8 bit in 6502/65816 modes and 32 bit in x832 mode. 9) The purpose of the VEC instruction is to simplify the trampoline from one mode to another. >>> Relocate code easily with the REL instruction. > REL $x,$y * $x and $y are expected to be 32 bit in all modes. * CPU will pause all other execution and /ACT will go high until finished. * Relocatable code should be written so that all absolute references are normalized to $00000000+the offset in the code. * REL $00200000,$002FFFFF will go through the code searching for instructions that use absolute addressing and add the first argument of REL to it, causing it to point at the proper location inside the code. * Use ONLY on code blocks. Data embedded in the code could be corrupted if it includes opcodes that do absolute addressing. * Above instruction would be encoded: 42 BA 00 00 20 00 FF FF 2F 00 >>> Slave Mode Slave mode halts the processor and opens up its own RAM on the bus. This allows you to do anything with the processor's state, from reading and changing the configuration, to loading a program to be executed by the CPU, to bootstrapping it with no RAM connected to it at all. You can (and should) also send the CPU's current clock speed this way, and set its internal RTC. To invoke slave mode: 1) Bring both ABM0 and ABM1 high. a) The current instruction will complete then the CPU will halt. 2) Wait for /ARW to go low (/RW will also go low). It is now prepared to receive data. 3) Set the address bus, data bus, and byte enables to what you want to poke on the CPU. 4) Assert RAM assertion (RA). /ARW and /RW will go high when the write is complete. 5) Deassert RA. /ARW and /RW will go back to low when ready again a) Usually the above 3 steps will be able to be done every 3 cycles. 6) Repeat 3-5 until all the data you want to send to the CPU is sent. 7) Return ABM0 and ABM1 to the desired mode. a) The CPU will attempt to continue according where it left off. b) If you have changed the processor state (altering registers, PC, the direct page, etc) the CPU WILL continue as you have configured it. >>> Processor states and register files (Unfinished spec) The 65x832 has powerful new register functions that should alleviate the strain of having only 3 working re NOTE: The terms "Processor state" and "register file" are used interchangably in this document. A register file is just the first 16 bytes of a processor state. If an instruction says it operates on a register file, then it only operates on the register file part of a processor state. >>> WDM ($42) Extension (Potentially unstable spec) This normally acts as an instruction prefix that forces the (normally 8/16 bit) instruction to operate on fully 32 bit memory and registers. This prefix affects the following addressing modes: ABSOLUTE: When the instruction would normally take a 24bit long, it now takes a 32bit long. Only 24 bit absolutes can be promoted to 32bit. Other absolute instructions may be reused. ABSOLUTE,(X/Y): As above, except X and Y are also 32 bit. The absolute address size is considered by the original instruction addressing mode. (ABSOLUTE): The address at the argument given is interpreted to be a 32 bit address. [ABSOLUTE]: Both the argument and the address at the argument address are considered 32bit. (ABSOLUTE,X): The X index and the location at the the destination address are considered 32 bit. The absolute address size is considered by the original instruction addressing mode. ACCUMULATOR: The accumulator is considered to be 32 bit. DIRECT: Does not affect direct page accessing. These instructions may be reused. If not reused it will execute like its un-prefixed instruction. DIRECT,(X/Y): X and Y are unconditionally considered 16 bit, even in 8 bit mode, since direct page can't be more than 64k. (DIRECT): The target address is considered to be 32 bit. [DIRECT]: Both the source and target address are considered to be 32 bit. (DIRECT,X): The target address is considered to be 32 bit. (DIRECT),Y: The target address is considered to be 32 bit. [DIRECT],Y: The source, target and Y are all considered to be 32 bit. IMMEDIATE: The argument is considered 32 bit. IMPLIED: May be reused for new instructions. If not reused, All implied arguments are considered 32 bit. LONG: All arguments are considered 32 bit. LONG,X: All arguments are considered 32 bit. RELATIVE8: Relative argument considered 24 bit. RELATIVE16: Relative argument considered 32 bit. SRC, DST: Both arguments considered 32 bit. STACK,S: S is considered 16 bit even in 8 bit mode. (STACK,S),Y: S is unconditionally considered 16 bit and Y is considered 32 bit. > Instruction suffixes: .B Byte (8 bit) operand/data65 .S Short (16 bit) operand/data .L Long (32 bit) operand/data .2 Second status register Instructions reused: 42 00: FPU $xxxxxxxx Reserved for future (possible) FPU instructions 42 02: COP $xxxxxxxx Call coprocessor. 42 08: PHP.2 Push second status register 42 0B: PHD.S Push 16 bit direct page register 42 18: DIV A,Y A/Y divided as 32 bit, X=Quotient, Y=Remainder 42 1B: PKR/PUR $x Pick/Put registers from register stack (without popping) 42 28: PLP.2 Pull second status register 42 2B: PLD.S Pull 16 bit direct page register 42 38: MUL X,Y X*Y multiplied together as 16 bit, result to 32 bit Acc 42 3B: PHR/PLR $x Push/Pull registers from register file stack 42 40: RTV Return from vector service 42 42: xx More instructions (when not assigned, acts as NOP) 42 4B: PHK.S Push 16 bit K register 42 58: DIV ($x32),Y (32bit loc)/Y divided as 32 bit, X=Quotient, Y=Remainder 42 5B: SEN.L Switch Endian 32 bit (aabbccdd->ddccbbaa) of accumulator 42 60: INP.L $xxxxxxxx Receive I/O port to accumulator. (32 bit read) 42 62: INP.S $xxxxxxxx Receive I/O port to accumulator. (16 bit read) 42 68: OUT.L $xxxxxxxx Send accumulator to I/O port. (32 bit write) 42 6B: OUT.S $xxxxxxxx Send accumulator to I/O port. (16 bit write) 42 78: MUL ($x32),Y (32bit loc)*Y multiplied together as 16 bit, result to 32 bit Acc 42 7B: SEN.S Switch Endian 16 bit (aabbccdd->bbaaddcc) of accumulator 42 8B: PHB.S Push 16 bit data bank register 42 9A: REG $x[,$y] Operate on register files / processor states. See below. 42 AB: PLB.S Pull 16 bit data bank register 42 B8: SEN.B Switch Endian 8 bit (aabb->bbaa) of 16 bit accumulator 42 BA: REL $x,$y Relocate code: See below 42 C2: RPS $x,$y Operate on processor state stack, as below 42 CB: SWN Swap Nybbles (ab->ba) 42 D4: INP.B $xxxxxxxx Receive I/O port to accumulator (8 bit read) 42 D8: GEP Get both processor status registers to C 42 DB: LDR/STR $x,$y Load/Store register from register file/storage 42 E2: SEP Set both processor status registers from C 42 EA: NOP #$xx Pause for #xx cycles 42 EB: XBA.L Exchange accumulator bits 16-31 with 0-15 42 F4: OUT.B $xxxxxxxx Send accumulator to I/O port (8 bit write) 42 F8: MMU $xxxxxxxx Reserved for MMU instructions 42 FB: XCE.2 Exchange carry and 32 bit mode flag. >> Processor configuration instructions: 42 42 08: CWP $xx: Clear write protect on CPU memory area page $xx 42 42 09: SWP $xx: Set write protect on CPU memory area page $xx 42 42 DB: SPD #xx Set PHI 0 output divisor (from the reference phi2 clock) 42 42 CC: SRC #xxxxxxxx Set reference clock speed (Does not change CPU speed should be set to the speed of the phi2 input clock) THIS SHOULD BE KEPT UP TO DATE by the system if the phi2 signal changes. 42 42 EA: NOP #xxxx.yyyy NOP for xxxx seconds and yyyy/65536 seconds. Does not enter the low power state. 42 42 CB: WAI #xxxx.yyyy Wait for an interrupt for xxxx seconds and yyyy/65536 seconds. Enters the low power state while waiting (like STP) 42 42 9A: TRA Transfer current register file pointer to A 42 42 C2: RSA Transfer register stack pointer to A 42 42 FB: CRM $xxyyzzzz CPU RAM Mode xx: Addressing space to configure: 00=$0000-$FFFF (16); 01=$FF0000-$FFFFFF (24); 1x=$FFFF0000-$FFFFFFFF (32) yy: CPU RAM to expose: 00=$FFF0-$FFFF (16B); 01=$FF00-$FFFF (256B); 10=$F000-$FFFF (4096B); 11=$0000-$FFFF (64K) Default=(16) $FF00-FFFF; (24) $[FF]F000-$[FF]FFFF; (32) $[FFFF]0000-$[FFFF]FFFF >> Instruction format for LDR/STR/PHR/PLR > LDR/STR (42 DB dox yz) $d: Direction (0=Load/Pop/Pick; 1=Store/Push/Put) $o: Operations 00 = No-op 01 = OR 10 = AND 11 = Swap $x: 00001 = A (Accumulator) 00010 = X (X register) 00100 = Y (Y register) 01000 = S (Stack pointer) 10000 = P (Processor status 1 and 2) 11111 = R (All registers. The above registers can be ANDed) 00000 = T (Entire processor state) $y: Source (0=register file; 1=register storage) $z: Register file (0-7 ----xxx) or Register storage (0-127 xxxxxxx) > PHR/PLR (42 3B dox) - Pushes/Pulls registers from reg stack * PHR and PLR will affect the reg stack pointer accordingly > PKR/PUR (42 1B dox) - Picks/Puts registers on top of reg stack * PKR and PUR do not affect the stack pointer. Picks and pulls can operate on the top of the stack repeatedly, and even change it for something that may push or pop it later. > Examples: LDR A,3 Load accumulator from register file 3 STR X,6 Store X to register file 6 LDR AXY,4 Load A X and Y from register file 4 STR R,?$33 Place all registers into register storage $33 PHR T Shove the entire processor state onto the reg stack PLR T Restore the processor state from the stack PLR R Restores only the registers from the stack PKR AXY Restores only A X and Y from the top of the reg stack and does not pop the processor state off. >> Register file instruction format (REG class) > xxx and xxxy here refer to register files or entire processor states (0-7) CPR x,y (42 9A 00xxxyyy): Copy register file from X to Y CPP x,y (42 9A 01xxxyyy): Copy entire processor state from X to Y SWI x (42 9A 10000xxx): Switch to register file X as main registers, bring current processor state SWP x (42 9A 10001xxx): Switch to register file X as main registers, adopt files' processor state CCR x (42 9A 10010xxx): Copy current registers to X, do not switch to X CSR x (42 9A 10011xxx): Copy current registers to X, then switch to X CCP x (42 9A 10100xxx): Copy entire processor state to X, do not switch to X CSP x (42 9A 10101xxx): Copy entire processor state to X, then switch to X ZRG x (42 9A 10110xxx): Fill register file X with zeroes ZPS x (42 9A 10111xxx): Fill entire processor state X with zeroes CSR x,y (42 9A 11xxxyyy): Copy registers from X to Y then switch to Y >> Timer instructions: 42 42 5t: HPT.$x $yy Sets timer $x to call vector $yy every $zzzz.zzzz seconds. CPU only allows 0-13 to be set this way. zzzz.zzzz is loaded from the accumulator and is expressed in 1/65536 seconds. x bit 3: 0=one shot; 1=continuous. x bit 2-0: continuous t: bits 2-0: timer # 42 42 5E LTD Load TOD from the 64bit unix TOD clock to X+Y (x LSL, y MSL) 42 42 5F STD Store X+Y to the 64bit unix TOD clock. >> Status register changes: P (or P1 or PL): No changes --------------------------- N #$80 10000000 Negative V #$40 01000000 Overflow M #$20 00100000 Accumulator register size (native mode only) (0 = 16-bit, 1 = 8-bit) X * #$10 00010000 Index register size (native mode only) (0 = 16-bit, 1 = 8-bit) B * #$10 00010000 Break (emulation mode only) D #$08 00001000 Decimal I #$04 00000100 IRQ disable Z #$02 00000010 Zero C #$01 00000001 Carry (XCE will exchange carry and Q register bit 6) Q (or P2 or PH): New status register ------------------------------------ EM #$C0 xx000000 Mode (00=6502, 01=65816, 10=65832[Via $42 prefix, cleared next instruction], 11=65x832[Via mode switch]) M32 #$20 00100000 Accumulator/Memory (1=32 bit, 0=by M flag) X32 #$10 00010000 Index regs (1=32 bit, 0=by X flag) B #$08 00001000 Break (Native mode) SV #$04 00000100 Inside service vector routine AE #$02 00000010 Arithmetic error (Division by Zero/FPU) IP #$01 00000001 Operation off bus >> CPU memory map of CPU internal RAM (SRAM or BRAM) $00000000-$0000FFFF Preferred Direct Page (also 6502/6510/8502 emulation space, user routines) $00010000-$0001FFFF Preferred 65816/65832 stack $00020000-$0002FFFF User applications (Speed critical or bus independant functions) $FFFF0000-$FFFFFFFF CPU use >> NOTE: The CPU can function entirely without RAM, just tie BE to ground and it will boot on its SRAM. >> See "Bootstrapping without RAM" above. >>> Register file and processor state format (used extensively in the CPU data area!) $00*16 Register file $00*32 Processor state >> Register file (first 16 bytes) $00 4 Accumulator (A) $04 4 X register (X) $08 4 Y register (Y) $0C 2 Stack register (S) $0E 1 Processor status register 1 (P / P1 / PL) $0F 1 Processor status register 2 (P2 / PH) >> Processor state is INCLUSIVE of register file and includes these 16 bytes also $10 2 Direct register (D) $12 4 Program Counter (PC) $16 2 Program Bank Register (PBR) $18 2 Data Bank Register (DBR) $1A 2 K Register (K) $1C 4 Reserved (but saved and restored) >>> CPU memory area (Base address $FFFFxxxx in ABM00/11 , $FFxxxx in ABM10, inaccessible in ABM01) $0000 49152 User functions or ROM mirror $C000 4096 128*32 Processor state storage $D000 4096 128*32 Processor state stack $E000 4096 16*256 Direct Page switch areas $F000 1024 256*32bit vectors (VEC $00-$FF) >>> CPU memory area (L1 Cache) $F400 1024 Used for caching purposes >>> CPU memory area (Absolute Direct Page) $F800 256 Absolute Direct Page >>> CPU memory area (8 bit mode) >> 6510/8502 mode $F940 1 P0-P7 port direction register $F941 1 P0-P7 state >>> CPU memory area (FPU registers/state) $FA00 256 Reserved for future use >>> CPU memory area (MMU registers/state) $FB00 256 Reserved for future use >>> CPU memory area (Timers) $FCx0 * 16*16 Timer x status: $x0 1 bit 7: 0=one shot; 1=continuous bit 6: 0=no alarm; 1=alarm bit 5: 0=disabled; 1=enabled bit 4: 0=call immediately; 1=save processor state first (processor state will be restored on RTV) bit 3-1: 000=Call vector on alarm (Expect RTV) 001=JSR to address on alarm (Expect RTS) 010=JMP to address on alarm (Expect not to return) 011=Treat as IRQ (expect RTI) 100=Decrement value at given address 101=Increment value at given address 110=Jump to address at vector expecting not to return (usually used to switch tasks) 111=Treat as NMI bit 0: Synchronized clock (Synchronize to a second) $x1 1 Vector to call on alarm $x2 2 Synchronize: Cycles left to successful sync $x4 4 Address to call on alarm $x8 4 Timer duration in 1/65536 sec $xc 4 Current timer tick (decremented every 1/65536 sec) Alarms on 0, resets on continuous. NOTE: When a timer is set to synchronize to the clock, the timer will load ($FD20:15-0) to $FCx3 and recheck and decrement $x3 every 256 cycles. When $x3 becomes 0, it will check and decrement $ $x2 every cycle until it is 0, then the alarm will go off. Synchronized timers go off every x/65536 seconds, while unsynchronized go off every x*(refclock/65536) cycles. Synchronized timers require more CPU resources, so only timers that need to be synced to an actual second or fraction thereof, should be driven by a synced clock. $FC00 Timer 0 : For application use $FC10 Timer 1 : For application use $FC20 Timer 2 : For application use $FC30 Timer 3 : For application use $FC40 Timer 4 : For application use $FC50 Timer 5 : For application use $FC60 Timer 6 : For application use $FC70 Timer 7 : For application use $FC80 Timer 8 : Recommend for OS/System use $FC90 Timer 9 : Recommend for OS/System use $FCA0 Timer 10 : Recommend for OS/System use $FCB0 Timer 11 : Recommend for OS/System use $FCC0 Timer 12 : Recommend for OS/System use $FCD0 Timer 13 : Recommend for OS/System use $FCE0 Timer 14 : DO NOT USE (Internal RTC uses this) $FCF0 Timer 15 : DO NOT USE (WAI and NOP use this) >>> CPU memory area (Processor state) $FD00 1 Processor state stack pointer $FD01 1 Register file stack pointer $FD08 8 64 bit cycle counter $FD10 4 Saved address bus state before invoking coprocessor $FD14 4 Saved data bus state before invoking coprocessor $FD18 4 Saved address bus state before invoking port access $FD1C 4 Saved data bus state before invoking port access $FD20 4 Reference clock speed in cycles (up to 4.2ghz) The timers are checked every ($FD20:31-16) cycles. DO NOT USE this as a perfectly accurate clock unless your input clock, clocks at a multiple of 65536. It will drift every second by ($FD20:0-15) cycles every second otherwise. Use a synchronized timer instead. $FD24 1 Phi2->Phi0 clock divisor $FD30 1 Current processor state (expressed as xxx00000) $FD31 1 Current processor state stack pointer $FD40 1 Boot status: 00=Power applied; FF=Fully booted Bit 7: /RESET is asserted Bit 6: Desired boot mode determined from reading lines Bit 5: Desired processor mode determined Bit 4: $FDC0 * 16 RTC fron timer 14 ($FDD0 should be initialized) $FDC0 8 Seconds (Unix 64 bit time_t) $FDC8 2 65536th's of a second $FDCA 6 Uptime (Seconds) $FDE0 32 CPU memory instruction write protect 256 bits (1 per 256 byte page) of CPU memory area to write protect $FFFFxx00-$FFFFxxFF. This does Not mean they cannot change, but only the CPU internals can change them, not instructions operating on them. Use this functionality to protect data in the CPU area, such as an area that should function as ROM. By default, $0000-7FFF is not protected, $8000-FFFF is. >>> CPU memory area (Registers and processor states) $FE00 32 Processor state 0 (Default main processor registers) $FE20 32 Processor state 1 $FE40 32 Processor state 2 $FE60 32 Processor state 3 $FE80 32 Processor state 4 $FEA0 32 Processor state 5 $FEC0 32 Processor state 6 $FEE0 32 Processor state 7 >>> CPU memory area (RAM/ROM) $FF00 176 CPU bootstrap RAM/ROM (provided by system) $FFB0 8 Used by MUL/DIV $FFB8 1 PBR for 16 bit vector calls $FFB9 3 16->8 retpoline (called when going from 16 to 8 bit mode if != $FFFFFF | $000000) $FFBC 4 32->8 retpoline (called when going from 32 to 8 bit mode if != $FFFFFFFF | $00000000) $FFC0 4 (32b mode) Named interrupt handling vector (Vector for interrupt that passes data on the bus) $FFC4 4 (32b mode) Port IRQ vector (Vector for interrupt invoked during a port transaction) $FFC8 4 (32b mode) COP vector ($FFFFFFFF for VEC support, else desination of 02 xxxxxxxx) $FFCC 4 (32b mode) BRK vector $FFD0 4 (32b mode) Abort vector $FFD4 4 (32b mode) NMI vector $FFD8 4 (32b mode) Extended COP vector (Destination of 42 02 xxxxxxxx) $FFDC 4 (32b mode) IRQ vector (Standard or vector pull mode) $FFE0 2 (16b mode) Named interrupt handling vector (as above) $FFE2 2 (16b mode) Port IRQ vector (as above) $FFE4 2 (16b mode) COP vector ($FFFF for VEC support, else destination of 02 xx) $FFE6 2 (16b mode) BRK vector $FFE8 2 (16b mode) Abort vector $FFEA 2 (16b mode) NMI vector $FFEC 2 (16b mode) Reset vector (for 16/32 bit mode, located in $FFxxxx or $FFxxxxxx) $FFEE 2 (16b mode) IRQ vector (as above) $FFF0 2 (8b mode) Named interrupt handling vector $FFF2 2 (8b mode) Port IRQ vector $FFF4 2 (8b mode) COP vector ($FFFF for VEC support, else destination of 02 xx) $FFF6 2 (8b mode) 8->16/32 retpoline (called when going from 8 to 16/32 mode if != $FFFF | $0000) $FFF8 2 (8b mode) Abort vector $FFFA 2 (8b mode) NMI vector $FFFC 2 (8b mode) Reset vector $FFFE 2 (8b mode) IRQ vector (BRK in 8 bit mode)