// Current Memory map (best config): Minimig MiSTer // Amiga FPGA Type Usage // $00000000-$001FFFFF $00000000-$001FFFFF SDRAM Chip RAM // $00200000-$00BFFFFF $00200000-$00BFFFFF SDRAM Z2 Fast // $00C00000-$00D7FFFF $00C00000-$00D7FFFF SDRAM Bogo // $00D80000-$00DFFFFF $00D80000-$00D8FFFF SDRAM Unusued (typically top half of 1MB ROM) // $00E00000-$00EFFFFF $00E00000-$00EFFFFF I/O Direct driven in tg68k.vhd // $00F00000-$00F7FFFF $00F00000-$00F7FFFF None Unusued (Typically expansion ROM / cartridge) // $00F80000-$00FFFFFF $00F80000-$00FFFFFF SDRAM Kickstart ROM // $40000000-$40FFFFFF $01000000-$01FFFFFF SDRAM Z3 Fast RAM (16mb) // $50000000-$5FFFFFFF $30000000-$3FFFFFFF DDR3 Z3 Fast RAM (256mb) // $60000000-$63FFFFFF $2C000000-$2FFFFFFF DDR3 Retargetable Graphics (RTG) (32mb) // MiniMig-Net - type Zorro II - Mapping probably $D9xxxx // - type C64-IO - Mapping $DFxx // - other cores to be determined Offset Size 0000 01 (READ) Status register 7-6: 11=24/32 bit mode, I/O buffer at offset $0100 10=24/32 bit mode, Pointer Buffer (PB) only 01=16 bit mode, Pointer buffer only 00=8 bit mode, byte interface only 3: 1=RXP New packet in progress 2: 1=ACK Packet / byte received by HPS 1: 1=BSY HPS Wait to send 0: 1=RX New packet sent / byte sent 0001 01 (WRITE) Control register 7-6: 11=24/32 bit mode, I/O buffer at offset $0100 10=24/32 bit mode, Pointer Buffer (PB) only (PB pointer is 32bit) 01=16 bit mode, Pointer buffer only (PB pointer is 16bit) 00=8 bit mode, byte interface (send 1 byte at a time to $0F) 2: 1=ACK Packet / byte received by CORE 1: 1=BSY CORE Wait to send 0: 1=TX New packet ready to send / byte ready 0002 02 MTU (up to 65280) | Byte interface: ignored 0004 02 MRU (up to 65280) | Byte interface: ignored 0006 02 Pointer to PB (0000=I/O buffer) 0008 02 MSB of PB (24/32 bit mode) 000A 02 (W) Size of data at pointer buffer (R) Size of payload written to PB 000F 01 Byte Interface: Byte to send/receive 0010 F0 Reserved -- addresses above 00FF not seen by 8 bit cores or cores with 16 bit addressing space 0100 65280 HPS mapped buffer (24/32 bit address bus only) Almost certainly shared with the top 64K of RTG (which won't be used)