VM65832-2012 -- Alynna Trypnotk, For use with the Kitsunet to 65816 translator Allows Magitech quantum computing to run programs that can be expressed in spatial dimensions. Please refer to 'brainfox.txt' for reference implementation. This is an emulator that runs on the Brainfox architecture. *** Incomplete - Not all instructions documented *** Specifications: Base CPU Emulation: 65816 extended: Base addressable memory: 16mb Extended addressable memory: 4080mb ( Total addressable RAM: 1020gb (16192k banks of 64kb) Total addressable I/O: 1tb (16m banks of 64kb) Total addressable ROM: 254tb (4064m banks of 64kb) Total addressing bits: 48 bits CPU addressing bits: 16 bits basic, 32 bits extended New registers: SS = 8 bit, specifies a 16mb bank within the bottom 4gb. AL = 32 bit accumulator, occupies the same space as A. Upper 16 bits cannot be accessed with standard 65816 instructions However the active accumulator can be swappped using an extended instructions. XY = 32 bit combination of X and Y. Accessible seperately as X and Y with standard 65816 instructions. X is the lower 16 bits of XY, Y is the upper 16 bits. ttrrssppbbbb: tt = Terabyte sized bank, byte 3 of page operand rr = 4 gigabyte selector, byte 2 of page operand ss = 16m segment selector, byte 1 of page operand pp = page (64kb) selector, byte 0 of page operand bbbb = byte within page Memory map: ttrrssppbbbb-ttrrssppbbbb 000000000000-00FFFFFFFFFF: 1tb RAM area (Mapped to as much system RAM as permitted, then mapped to SWAP as needed) 000000- FFFFFF: Directly addressable memory mapped area (Zero Selector, can be remapped by setting the BANK register) 01000000- FFFFFFFF: Extended Instruction addressable memory area (4032mb) Mapped to RAM first than SWAP, Mappable and bankable 000100000000-00FFFFFFFFFF: 1020gb Mapped RAM area (mapped to SWAP, cached to RAM, expired by least accessed) 010000000000-FFFFFFFFFFFF: 254tb Mapped ROM area (mapped to NETWORK, cached to RAM then SWAP, expired by least accessed -- CONSIDERED READ ONLY) FF0000000000-FFFFFFFFFFFF: 1tb I/O area FF0000000000-FF00FFFFFFFF: 4gb frame buffer FF0100000000-FF01FFFFFFFF: 4gb sprite buffer The SUPER addressing mode. The addressing mode 'Super' is indicated by an address with 4 bytes and can directly address any byte in the bottom 4gb of address space. They usually have 6 bytes. 2 bytes for the instruction, 4 for the operand. When doing a JSR to a new bank, the PC is incremented by 5, and the bank and incremented PC is stored on the stack in the destination bank. When returning, the 4 bytes are ripped off the stack, replacing the bank register and the PC. When the SUPER addressing mode refers to the accumulator, this means it will refer to all 32 bits of the accumulator, usable by the extended instructions. When the SUPER addressing mode refers to the X index register, it will also operate on Y as if Y were the upper 16 bits of X, using both as one index register. Instruction deviations from standard 65816 CPU 42 0bbbbbbb: MAP instruction (16 bit instruction) -- Map Pages: The second instruction xx specifies the instruction type: Up to 3 operands can be sent to MAP after the first two bytes. The bits in the second byte specify sizes and presence. Bit 7: 0=Other MMU instructions, 1=Map a page according to the bits 6-0 Bit 6: 0=Map pages, unmapping any pages that this mapping may overlap. 1=Unmap any pages this mapping would overlap. Bit 5: Source page bits: 0=Ommited bytes are assumed to be all bits clear (00), 1=Ommited bytes are assumed to be all set (FF) Bit 4: Number of bytes in destination page (0=8 bit (Directly addressable, 1=16 bit (Extended addressable) ONLY the bottom 4gb can have pages mapped into it! Bit 3: 0=Last parameter is page count, 1=Last parameter is ending page (16 bit value) Bit 2: 0=8 bit value within Directly Addressable area, 1=16bit in Mappable Area Bit 1-0: Number of bytes in source page (minus one, meaning 0-3 for 8 to 32 bits) Up to 3 operands can be sent, little endian, depending on the sizes specified above, in the order: Destination Page, Source page, number of pages (or ending page) Examples: ---4---2 ---0---1 01000010 00000002 42 1bbbbbbb: MMU instruction (16 bit instruction): MMU control 42 80: BNK xx 0x02 ** Prefix for extended instructions **: Inst Mneumonic Addressing mode / Description ----- --------- --------------- 02 00 SWP SUPER Swap 16 bit accumulators for 65816 instructions 02 02 COP xxxx Coprocessor 02 0F ORA $nnnnnnnn Absolute Super 02 3A INC SUPER Accumulator Super 02 1F ORA $nnnnnnnn,X Absolute Super Indexed, X 02 22 JSR $nnnnnnnn Absolute Super 02 2C BIT $nnnnnnnn Absolute Super 02 2F AND $nnnnnnnn Absolute Super 02 3A DEC SUPER Accumulator Super 02 3C BIT $nnnnnnnn,X Absolute Super Indexed, X 02 3F AND $nnnnnnnn,X Absolute Super Indexed, X 02 4F EOR $nnnnnnnn Absolute Super 02 5C JMP $nnnnnnnn Absolute Super 02 5F EOR $nnnnnnnn,X Absolute Super Indexed, X 02 6B RTX Stack Super 02 6F ADC $nnnnnnnn Absolute Super 02 7C JSR $(nnnnnn) Absolute Indirect Super 02 7F ADC $nnnnnnnn,X Absolute Super Indexed, X 02 80 STZ $nnnnnnnn Absolute Super 02 82 BRL $nnnnnn PC Relative Long 02 8F STA $nnnnnnnn Absolute Super 02 90 STZ $nnnnnnnn,X Absolute Super Indexed, X 02 92 BRS $nnnnnnnn PC Relative Super 02 9F STA $nnnnnnnn,X Absolute Super Indexed, X 02 AF LDA $nnnnnnnn Absolute Super 02 BF LDA $nnnnnnnn,X Absolute Super Indexed, X 02 CE DEC $nnnnnnnn Absolute Super 02 CF CMP $nnnnnnnn Absolute Super 02 DC JMP $(nnnnnn) Absolute Indirect Super 02 DE DEC $nnnnnnnn,X Absolute Super Indexed, X 02 DF CMP $nnnnnnnn,X Absolute Super Indexed, X 02 EC JMP $(nnnnnnnn) Absolute Super Indirect Super 02 E8 INX SUPER Implied Super 02 EE INC $nnnnnnnn Absolute Super 02 EF SBC $nnnnnnnn Absolute Super 02 FC JSR $(nnnnnnnn) Absolute Super Indirect Super 02 FE INC $nnnnnnnn,X Absolute Super Indexed, X 02 FF SBC $nnnnnnnn,X Absolute Super Indexed, X